UVM for FPGAs Seminar – Part 4 –
IEEE 1800.2 UVM updates
07 October 2021 3.00 p.m. to 4.00 p.m.
Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.
UFS stands for Universal Flash Storage. These specifications are developed jointly by the MIPI Alliance and JEDEC. Over time, UFS has evolved to support data rates from 5.8 Gbps per lane up to 11.66 Gbps data rate. Now MIPI Alliance and JEDEC are working on UFS4.0 with a data rate of 23.2 Gbit/s per lane to enable new applications in 5G, automotive, gaming and augmented reality. Validation and debugging of the UFS4.0 protocol with the MPHY HSG5B specification of 23.2 Gbps data rate and low power consumption is challenging due to the signal characteristics of the PHY layer and the data rate
Aldec Webinar Recording
- Why UVM?
- UVM- Top-down and Bottom-up View
- UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
- Aldec solutions and live demo
- Using UVM for VHDL designs
- Port mapping rules and FPGA flow
- Binding SVA assertions to VHDL
- TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
- Zynq MPSoC design characteristics
- Introduction to UVM RAL and anatomy of UVM register models
- Auto-generation of RAL models
- Adapter modeling in UVM RAL
Agnisys Webinar Recording
IDS-NG is a unified system for SoC design. It provides fully verified and validated IPs with their standard configurable APIs and takes you from the IP level to the system level.