Events

Free Webinar

FPGA Verification Architecture Optimization with UVVM

05. May 2022 – 3.00 to 4.00 pm

FPGA Verification Architecture Optimization with UVVM

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.

Aldec Webinar Recording

FPGA Design Architecture Optimization

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.

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The most error prone FPGA corner cases

Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.

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UVM for FPGA

UVM for FPGAs (Part 1): Get, Set, Go - Being Productive with UVM

  • Why UVM?
  • UVM- Top-down and Bottom-up View
  • UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
  • Aldec solutions and live demo
UVM for FPGA

UVM for FPGAs Seminar Part 2 Solving FPGA Verification Problems with UVM

  • Using UVM for VHDL designs
  • Port mapping rules and FPGA flow
  • Binding SVA assertions to VHDL
  • TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGA

UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help

  • Zynq MPSoC design characteristics
  • Introduction to UVM RAL and anatomy of UVM register models
  • Auto-generation of RAL models
  • Adapter modeling in UVM RAL

Agnisys Webinar Recording

IDS-NG for automatic verification

IDS-NG for automatic verification

No more waiting for the verification team. Verify your design quickly with an automatically generated verification environment.

IDS-NG for Design

IDSNextGen™ (IDS-NG) for Design

IDS-NG is a unified system for SoC design. It provides fully verified and validated IPs with their standard configurable APIs and takes you from the IP level to the system level.

IDS-NG for Firmware

IDSNextGen™ (IDS-NG) for Firmware

Create programming and test sequences that can be used from early design and verification through to post-silicon validation.

Prodigy Technovations Webinar Recording

Prodigy I3C Conformance Test Solution

I3C Conformance Test Solution

MIPI Alliance I3C specification has been widely adopted for many applications like mobile, automotive, gaming, and IoT.

Prodigy Technovations 100BASE-T1 Automotive Ethernet Webinar

100BASE-T1 Automotive Ethernet

100BASE-T1 Automotive Ethernet Protocol Analyzer has multiple features to capture and debug communication between host and design under test.

Prodigy Technovations embedded technology

Cross-protocol analysis with the Logic Analyzer

Debugging Embedded systems design is challenging. Each design has a unique set of requirements and constraints.