Events

Free Webinar

UVM for FPGAs Seminar – Part 4 –
IEEE 1800.2 UVM updates

07 October 2021 3.00 p.m. to 4.00 p.m.

UVM for FPGA

Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.

Free Webinar

Prodigy UFS 4.0

20 October 2021 – 9.30 to 10.30 a.m.

Prodigy UFS-4

UFS stands for Universal Flash Storage. These specifications are developed jointly by the MIPI Alliance and JEDEC. Over time, UFS has evolved to support data rates from 5.8 Gbps per lane up to 11.66 Gbps data rate. Now MIPI Alliance and JEDEC are working on UFS4.0 with a data rate of 23.2 Gbit/s per lane to enable new applications in 5G, automotive, gaming and augmented reality. Validation and debugging of the UFS4.0 protocol with the MPHY HSG5B specification of 23.2 Gbps data rate and low power consumption is challenging due to the signal characteristics of the PHY layer and the data rate

Aldec Webinar Recording

UVM for FPGA

UVM for FPGAs (Part 1): Get, Set, Go - Being Productive with UVM

  • Why UVM?
  • UVM- Top-down and Bottom-up View
  • UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
  • Aldec solutions and live demo
UVM for FPGA

UVM for FPGAs Seminar Part 2 Solving FPGA Verification Problems with UVM

  • Using UVM for VHDL designs
  • Port mapping rules and FPGA flow
  • Binding SVA assertions to VHDL
  • TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGA

UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help

  • Zynq MPSoC design characteristics
  • Introduction to UVM RAL and anatomy of UVM register models
  • Auto-generation of RAL models
  • Adapter modeling in UVM RAL

Agnisys Webinar Recording

IDS-NG for automatic verification

IDS-NG for automatic verification

No more waiting for the verification team. Verify your design quickly with an automatically generated verification environment.

IDS-NG for Design

IDSNextGen™ (IDS-NG) for Design

IDS-NG is a unified system for SoC design. It provides fully verified and validated IPs with their standard configurable APIs and takes you from the IP level to the system level.

IDS-NG for Firmware

IDSNextGen™ (IDS-NG) for Firmware

Create programming and test sequences that can be used from early design and verification through to post-silicon validation.

Prodigy Technovations Webinar Recording

Prodigy I3C Conformance Test Solution

I3C Conformance Test Solution

MIPI Alliance I3C specification has been widely adopted for many applications like mobile, automotive, gaming, and IoT.

Prodigy Technovations 100BASE-T1 Automotive Ethernet Webinar

100BASE-T1 Automotive Ethernet

100BASE-T1 Automotive Ethernet Protocol Analyzer has multiple features to capture and debug communication between host and design under test.

Prodigy Technovations embedded technology

Cross-protocol analysis with the Logic Analyzer

Debugging Embedded systems design is challenging. Each design has a unique set of requirements and constraints.