Thursday 10. March from 3.00 pm to 4.00pm

Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification techniques such as constrained random verification with assertion-based verification (ABV) can be used to help identify ambiguous or incomplete requirements early in the design and verification process. The ability of assertions to increase the observability of the design can dramatically reduce debug time. Reducing the time spent debugging increases the time that can be spent searching for new bugs, leading to better verification quality.

In this webinar, Aldec presents how to optimize and verify requirements using SystemVerilog Assertions (SVA)


  • Introduction to requirements-based verification
  • Verification completeness
  • Coverage usage and types
  • Assertions-based verification
  • Assertions planning and definitions
  • Developing functional coverage with SVA
  • Checking design requirements with SVA
  • Using SVA for RBV
  • SVA for developing design requirements
  • SVA for specifying RTL code properties
  • SVA to increase design observability
  • Achieving completeness in requirements verification

The most error prone FPGA corner cases

Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.

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