FPGA Simulation
Functional Verification
Emulation & Prototyping
Requirement Management
Mil/Aero Verification
Aldec, Inc.
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in developing complex FPGA, ASIC, SoC and embedded system designs. The quality of the products and the customer-oriented support particularly characterize Aldec. With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.
Essential steps to simplify VHDL testbenches with OSVVM
This Getting Started webinar focuses on the first, essential steps you need to take if you want to improve your VHDL testbench approach with OSVVM.
Checking AXI connections with ALINT-PRO and Riviera-PRO
AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses...
Effinix and Aldec Active-HDL promotion
Active-HDL Designer Edition Perpetual License – Request a quote! Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments.
Riviera-PRO supports OpenCPI for heterogeneous embedded computing
Aldec supports the Open Component Portability Infrastructure (OpenCPI) with the latest version of Riviera-PRO (version 2022.04).
FPGA Design – Verification Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, which is a great combination.
FPGA Verification Architecture Optimization with UVVM
How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.
FPGA Design Architecture Optimization
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.
Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types
The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification.
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
Increase your productivity with Continuous Integration flows
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to...