FPGA Simulation
Functional Verification
Emulation & Prototyping
Requirement Management
Mil/Aero Verification
Aldec, Inc.
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in developing complex FPGA, ASIC, SoC and embedded system designs. The quality of the products and the customer-oriented support particularly characterize Aldec. With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.
Riviera-PRO supports OpenCPI for heterogeneous embedded computing
Aldec supports the Open Component Portability Infrastructure (OpenCPI) with the latest version of Riviera-PRO (version 2022.04).
FPGA Design – Verification Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, which is a great combination.
FPGA Verification Architecture Optimization with UVVM
How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.
FPGA Design Architecture Optimization
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.
Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types
The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification.
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
Increase your productivity with Continuous Integration flows
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to...
Aldec Riviera-PRO™ UVM-Generator
Riviera-PRO™ has been enhanced with an automatic UVM generator function The addition promises to significantly increase the productivity of Riviera PRO users who take advantage of the Universal Verification Methodology, which provides guidance for creating and reusing verification testbenches.
Constraint Random Verification with Python and Cocotb
Cocotb, an approach to using Python as a testing language, allows developers to start with small, directed test benches and evolve them into more thorough constraint random tests.
Using OVL for Assertion-Based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal...