A Complete Automated Verification System

Agnisys Generated UVM Testbench from Specta-AV

Specta-AV™ is a comprehensive UVM testbench generator that automates verification using industry-proven code generation technology. With the ability to parse hierarchical register specification from IP-XACT, SystemRDL, Word, or Excel, and the capability to retarget complex sequences into various modeling language such as C and SystemVerilog, Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for autogenerating UVM tests/environments/agents.

With Specta-AV, the generation of the complete UVM testbench, including sequence items, configurations, checkers, coverage, and even the plumbing within UVM, is automated not just for addressable registers but for your application (user) logic as well.

Automation with Specta-AV provides 100% functional coverage out of the box with register-focused cover groups that is the key to verification success as IPs and SoCs grow in complexity.

The tool flow consists of three main parts:

The user specifies register and memory map definitions, functional and test sequences for custom IPs, UVM configurations, checkers, and coverage of interest

The user specifies commercial protocol VIPs and instantiates the user design module

The user generates the following code:

  1. Register RTL, UVM model, or HTML
  2. Bus interface logic: AXI, APB, AHB, or proprietary
  3. UVM environment, sequences, checkers, cover groups, and assertions
  4. Simulation makefiles


  • An order of magnitude less code entered manually; the rest is automatically generated
  • Automatic creation of a verification environment and tests according to the specification
  • UVM expertise helpful but not required
  • Ideal for startups learning UVM and for large organizations intending to streamline verification
  • Promotes vertical and horizontal reuse of tests and environment