Advanced SoC verification tool
Automation that provides 100% coverage is key to verification success as IPs and SoCs grow in complexity.
Based on the register specification, Automatic Register Verification (ARV™) generates the complete UVM testbench: bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences, as well as the Makefile and Verification Plan. The UVM testbench is fully connected to the UVM Register Model and DUT, providing you with a push-button verification.
Sequences are automatically generated for various types of register behaviour. These sequences are called out by a virtual sequence based on the access type of the fields. You can generate First-Level Sequences for the fields, Register-Level Sequences for registers and positive/negative sequences for Special Registers.
Verification via Simulation and Formal
Verification can be done using complementary verification methodologies. The generated files include “Makefiles” for the industry popular simulations and formal tools. In addition to direct and constrained random simulation test cases, the entire verification process can be further improved by formally verifying IPs with the slave interface, reducing simulation runs and overheads involved in creating block-level test benches.
Verification Plan and Coverage Report
The generated graphical report includes a Verification Plan showing the complete summary of the coverage results and test status. The hierarchy of the IP, along with functional coverage, is displayed in HTML format. The data is depicted with various colours to easily get the percentage of the pass and failure of the coverage. The Zoom functionality helps you focus on a specific component and its internal hierarchy.
The software writes access to a register can be locked based on another register field’s value or an expression consisting of different registers or fields.
Some registers are not directly accessible via a dedicated address. Indirect access of an array of such registers is accomplished by first writing an “index” register with a value that specifies the array’s offset, followed by a reading or writing of a “data” register to obtain or set the value for the register at that specified offset. See the logical view of Indirect register with ARV:
ARV automatically generates all of the callback classes into the register model, also generates UVM sequences for special registers like Shadow Register, RO-WO pair at the same address, Aliased Register, Locked Register, Trigger-Buffer Register (Wide register), Indirect Register, Interrupt Fields/Registers, Counters, FIFO Register, Paged Register, External (User Defined) Registers etc.
ARV-Formal™ is a complete solution that takes the register specification and RTL design as input and performs formal proof to ensure all register operations conform to the specification. ARV-Formal is powered by an embedded version of (OneSpin 360® DV Verify) to provide a one-button seamless process flow leveraging the power of modern formal verification tools. ARV-Formal automatically generates assertions directly from the specification, therefore completely automating the setup and ensuring a rapid investment return. Users are using the ARV Formal output with Mentor Questa® Formal.
ARV-Sim™ is a complete register verification solution that integrates with Synopsys VCS®, Cadence Incisive® and Mentor Questa® simulators. ARV-Sim automatically generates the complete package including bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences required for System Verilog (SV), Universal Verification Methodology (UVM) testing. It creates the simulator make-files to automate the verification process completely. This approach eliminates the lengthy and error prone UVM test bench and sequence creation process. ARV-Sim automatically provides the positive and negative sequences – not just the test bench but also the actual test sequences that stimulate the hardware to ensure that the implementation is correct.