UVM Register Model Generation
System RDL and IP-XACT Compiler
Automatically generate UVM Sequences
Advanced SoC Verification Tool
Agnisys Inc.
Agnisys Inc. is a leading provider of Electronic Design Automation software for solving complex design and verification problems in system development. The products provide a common, specification-driven development flow for describing registers and sequences for System-on-Chip and IP’s (Intellectual Property), enabling faster design, verification, firmware and validation. Agnisys is headquartered in Boston, Massachusetts, and has R&D centres in the United States and India.
Specification Automation for Designers
Requirements for various project teams and various tasks in the System-on-Chip (SoC) development process: hardware design, simulation, formal verification, firmware coding, system-level validation, and more.
A high quality standard for standards-based IP
The Standard Library of IP Generators (SLIP-G™) has proven to be very popular with users, and this is not surprising. Reuse plays a significant role in system-on-chip (SoC) development.
Automating the UVM Register Abstraction Layer (RAL)
This post focuses on the UVM Register Abstraction Layer (RAL), sometimes called the UVM Register Layer. Today’s large system-on-chip (SoC) designs contain many control and status registers, often accessible from embedded software or drivers as well as hardware.
Automation of IP and SoC development
Agnisys has expanded its original focus on register automation to encompass specification-driven design, verification, embedded programming, validation, and documentation of IPs and SoCs This expansion is a testament to Agnisys growth and the many challenges semiconductor development teams face.
Webinar on Embedded System Development Using Agnisys
Embedded System Development Using Agnisys This provides a path that avoids many pitfalls present in a typical flow, such as a slow process, duplicate efforts, wasteful resources, and so on.
Automatically translate English description into SystemVerilog Assertions
Agnisys has developed a unique approach that uses artificial intelligence (AI) and machine learning (ML) to translate English descriptions of design intent into SystemVerilog Assertions (SVA).