FPGA Design Architecture Optimization

PGA Design/Verification Best-Practices for Quality and Efficiency

28 April 3:00 PM – 4:00 PM

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload and a high degree of detected and undetected bugs. Most design architectures can be improved and optimized to increase both quality and efficiency.

The FPGA design architecture also affects several projects and product characteristics such as reusability, power consumption, resource usage, timing closure, clocking issues, implementation clarity, review easiness, and verification/test workload.



  • State of the FPGA community
  • Examples of bad FPGA design architectures (results and disadvantages)
  • How to improve and optimize FPGA design architectures (results and advantages)
  • How design and design changes can be simplified

The most error prone FPGA corner cases

Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.

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