IDSNextGen™ (IDS-NG) is a multi-platform product that helps users create SoC specifications at the enterprise level. It handles individual IP to subsystem to SoC level and is compatible with Word, Excel, IP-XACT, RALF, CSV, and SystemRDL. IDS-NG generates design and verification code for both registers and sequences in one integrated environment. It helps to improve the productivity of FPGA/ASIC, IP/SoC, and System Development teams.
Agnisys products encompass an innovative register information management system to capture hardware functional specifications and addressable register specifications in a single “executable” specification. All downstream code and documentation for the addressable registers, sequences, interrupts, hierarchical aggregators, or SECDED can be generated from this single specification. This eliminates the inefficiencies around specifications in the digital design process and helps reduce the design cost while improving quality and time to market. SLIP-G (Standard Library of IP Generators) from Agnisys offers configurable standard IP generators as an extension to addressable register generation.
These IPs are designed to be easily customizable and configurable to meet any SoC requirements. IDS-NG automatically creates register specifications and generates RTL for standard IPs. SoC Enterprise (SoC-E)provides a flexible and customizable environment for SoC design assembly to comprehensively meet specific design requirements. It is not just an assembler as it can also generate RTL components such as bus aggregators, bus bridges (AHB-APB, AXI-APB, AXI4Full-AHBFull), muxes, and other “plumbing” components by leveraging the already existing and mature register solution.