Hardware development

Creating HDL Descriptions for ASIC and FPGA Designs

Whether you are working with VHDL or Verilog, you will find that hardware description languages are different from sequential programming languages because VHDL and Verilog are parallel languages specified for modelling hardware. As a rule, the design flow in hardware development for FPGA and ASIC components consists of input, simulation, synthesis, place & route, and validation of the chips.

eVision Systems Design Flow
In general, unnecessary iterations in the design flow should be avoided. The reason for this is that errors are more expensive the later they are found. An error on code level can be corrected much faster by a direct error message during input or compilation than an error found during prototyping. That only becomes visible when SW and HW interact. Our goal is to provide tools that help you find bugs as early as possible in the design flow and avoid unnecessary iterations.

At the beginning of the development process in hardware development there is the HDL code description. There are several basic decisions to be made here:

  • What language (VHDL, Verilog, System Verilog, SystemC)?
  • Should it be a monolingual design or a mixed-language design (e.g. VHDL for the own blocks and Verilog for IP blocks of the FPGA manufacturers)?
  • Are all blocks described textually or should a graphic tool also be used?

We would be happy to help you evaluate the advantages and disadvantages. Simply contact us at support@evision-systems.de and we will get in touch with you.

You can find more information about the different input tools on our HDL Design page.

HDL Design
eVision Systems Design Flow

Verifying HDL code in hardware development

To find errors in the design in time, there are several verification methods. First, static methods can determine whether the code is written correctly in terms of syntax and semantics and whether there are structural problems within the code. However, functional aspects cannot usually be taken into account here.

To check the function of a code, either so-called property checks are carried out, or the code is simulated with corresponding test sequences in the simulator. Various hardware description languages are available for this purpose, such as VHDL or SystemVerilog.

HDL Verification