Creating HDL Descriptions for ASIC and FPGA Designs
Whether you are working with VHDL or Verilog, you will find that hardware description languages are different from sequential programming languages because VHDL and Verilog are parallel languages specified for modelling hardware. In normal cases, the design flow for FPGA and ASIC components consists of input, simulation, synthesis, place&route, validation of the chips.
At the beginning of the development process is the HDL code description. There are several basic decisions to be made here:
- What language (VHDL, Verilog, System Verilog, SystemC)?
- Should it be a monolingual design or a mixed-language design (e.g. VHDL for the own blocks and Verilog for IP blocks of the FPGA manufacturers)?
- Will all blocks be described textually, or should a graphical tool also be used?
We will be happy to help you evaluate the advantages and disadvantages. Contact us at firstname.lastname@example.org, and we will get in touch with you.
You can find more information about the different input tools on our HDL Design page.