Creating HDL Descriptions for ASIC and FPGA Designs
Whether you are working with VHDL or Verilog, you will find that hardware description languages are different from sequential programming languages because VHDL and Verilog are parallel languages specified for modelling hardware. In normal cases, the design flow for FPGA and ASIC components consists of input, simulation, synthesis, place&route, validation of the chips.
In general, unnecessary iterations in the design flow should be avoided. The reason for this is that errors are more expensive the later they are found. An error on code level can be corrected much faster by a direct error message during input or compilation than an error found during prototyping. That only becomes visible when SW and HW interact. Our goal is to provide tools that help you find bugs as early as possible in the design flow and avoid unnecessary iterations.
At the beginning of the development process is the HDL code description. There are several basic decisions to be made here:
- What language (VHDL, Verilog, System Verilog, SystemC)?
- Should it be a monolingual design or a mixed-language design (e.g. VHDL for the own blocks and Verilog for IP blocks of the FPGA manufacturers)?
- Will all blocks be described textually, or should a graphical tool also be used?
We will be happy to help you evaluate the advantages and disadvantages. Contact us at firstname.lastname@example.org, and we will get in touch with you.
You can find more information about the different input tools on our HDL Design page.
Verifying the HDL Code
To find errors in the design in time, there are several verification methods. First, static methods can determine whether the code is written correctly in terms of syntax and semantics and whether there are structural problems within the code. As a rule, however, functional aspects cannot be taken into account here.