When creating VHDL code, a lot of errors can happen. These can be simple typos, syntax errors, semantic errors or structural errors.
Especially errors that are not visible during the compilation of a single file can usually not be detected by the editor alone. Linting tools can be used to detect such problems in time. These also enable compliance with specially defined design rules. With Alint-Pro, ALDEC offers a linting tool for which various rule sets are available and enables cross-file checks such as CDC checks (Clock Domain Crossing).