FPGA Verification Architecture Optimization with UVVM

FPGA Design/Verification Best Practices for Quality and Efficiency

5. May 3:00 PM – 4:00 PM

For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.



  • Testbenches with basic architecture and their limitations
  • Components of an efficient and advanced testbench architecture
  • VHDL Verification Components (VVC)
  • Controlling and checking many interfaces simultaneously
    UVVM, VVC Framework Testbench Sequencer

The most error prone FPGA corner cases

Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.

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