FPGA Verification Architecture Optimization with UVVM
FPGA Design/Verification Best Practices for Quality and Efficiency
5. May 3:00 PM – 4:00 PM
For most FPGA projects, over 50% of the overall project time is spent on verification. This time can be significantly reduced if the verification architecture is well-structured and developed with a focus on reuse. In this webinar, we will show you how to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture. We will also discuss the importance of testbench sequencer simplicity and how it can be used to control multiple VHDL Verification Components simultaneously.
- Testbenches with basic architecture and their limitations
- Components of an efficient and advanced testbench architecture
- VHDL Verification Components (VVC)
- Controlling and checking many interfaces simultaneously
UVVM, VVC Framework Testbench Sequencer
FPGA Design – Verification Code, Functional and Specification Coverage
Functional coverage is often mentioned together with constrained-random verification, which is a great combination.
FPGA Design Architecture Optimization
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
Increase your productivity with Continuous Integration flows
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to...
Constraint Random Verification with Python and Cocotb
Cocotb, an approach to using Python as a testing language, allows developers to start with small, directed test benches and evolve them into more thorough constraint random tests.
Using OVL for Assertion-Based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal...
The most error prone FPGA corner cases
Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.
UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.