Automatic SOC Verification and Validation
A complete Integrated Software for SOC/IP teams aims to cut down the verification and validation time. ASVV automatically generates UVM and C sequences which exhaustively tests the Memories and register maps. ASVV also provide a way to generate custom tests for boards, UVM and UVM-C based environments through a common specification. It provides a complete solution to firmware Engineers to write and debug the device drivers and application software.
Automated test Generation:
- Positive and negative test for testing various register access types for UVM based environments.
- tests to check the functionality of special register like Lock register, Page register, Indirect Register which provides 100% coverage for UVM based environments.
- C and UVM tests to verify rw, wo and ro access of registers.
- C and UVM tests to verify the special registers like shadow, alias etc.
Custom Test Generation:
- Generates user-defined functional tests to verify the functional behaviour of a block.
- Configuration sequences can be used for testing as well as for device driver development.
- Single specification to generate tests for multiple platforms like UVM, UVM/C and boards.
- Python and excel based flow to write the test specification.
ASVV generates not only automated and custom tests but also generate various verification environments for running the same. ASVV generates three kind of environments:
- UVM environment for verification.
- UVM-C based SOC verification environment.
- Co-verification environment.
UVM environment for IP verification:
- Generates all essential UVM components along with an integrated RAL model.
- Generates UVM agents based on the configuration settings like axi, ahb etc.
- By default, a memory map is integrated for testing the generated rtl and sequences.
- Automated and custom generated tests get automatically integrated.
- It can be used as starting point for IP verification.
UVM-C based SOC verification environment:
- Generates UVM-C based environment which can run both C and UVM tests.
- RISC-V based SweRV Core EH1 rtl is integrated for running the C programmes.
- A synchronizer component is also generated, which provides synchronization between C and UVM tests.
- C programs are used to configure the IP blocks, whereas UVM tests can drive the ports and extra logic.
- Capable of handling interrupts and their ISR routines.
- Can be used as a starting point for developing a SOC verification environment.
- Can be used to test the connection b/w various IP blocks.
- Can be used to develop, debug the device drivers or software for various IP blocks.
- QEMU and UVM based environment capable of running C and UVM tests.
- QEMU is used for emulating the processor behaviour.
- Can be used to develop or debug the devices drivers for IP blocks.