With the increasing complexity of IP/SoC designs, the verification effort takes more and more time. From creating a verification environment, test sequences and configurations to plumbing every bit, many manual steps are required. IDS NextGen™ (IDS-NG) is a multi-platform product that helps users to write their own sequences with the help of ISequenceSpec™ (ISS) and generate automatic verification environments with the help of Specta-AV. Specta-AV is a superset of ARV and a comprehensive UVM testbench generator for IPs/SOCs. This tool automates verification using an industry-proven code generation technology. It can parse hierarchical register specifications from IP-XACT, SystemRDL, Word, or Excel, and retarget complex sequences into modelling languages such as SystemVerilog. Specta-AV facilitates a methodology where multiple SoC groups can align and work from a golden specification for auto-generating UVM Tests/Environments/Agents. With the help of ISS, users can write/generate their own custom UVM sequences and the generated sequences can be integrated in the automatic UVM verification environment.

IDS-NG for automatic verification

This webinar describes the steps to generate custom UVM sequences using ISS and how Specta-AV will include these and provide the best framework to generate complete UVM testbench including tests, sequence items, configurations, checkers, coverage, and all the connectivity automatically.