Usually, we are visiting DAC every year to meet our partners and customers. Since most of our customers have decided to avoid international travel and some of our partners did decide to skip their participation because of the pandemic situation we had some virtual meetings instead. One of the latest talks that Michael had was a discussion about ALDECs DO254 flow with Louie De Luna, international Sales Manager at ALDEC.
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As an EDA tool vendor, what is Aldec’s role in the commercial aviation market?
What was the initial trigger for Aldec to offer solutions to assist with DO-254 compliance?
Starting in 2005, when the FAA/EASA recognized DO-254/ED-80 as an acceptable design assurance guidance for FPGAs, we started to collaborate closely with our customers to determine what they need and how we can help. They needed new tool capabilities and solutions that can help them comply to the stringent verification process defined in DO-254. It was a natural progression for our company, and we stepped up to the challenge.
What does Aldec provide to help with DO- 254 compliance?
requirements capture, conceptual design, detailed design, validation and verification. The solution includes training, DO-254 templates and checklists, HDL graphical entry tools, HDL simulation, code coverage, linting based on best-practice HDL coding standards, clock domain crossing (CDC) analysis, traceability and in-target physical test systems. Our tools provide the most benefit to FPGAs with design assurance level (DAL) A or B classification because of the required verification activities needed for compliance.
What do you think is one of the critical issues in the verification process in the context of DO-254 compliance?
For designs with DAL A or B classification, the most difficult aspect regarding FPGA verification is the importance of requirements-based testing in the target board. One of the main challenges is the inability to verify specific requirements by physical test because testing the FPGA device at the board level provides very low FPGA input control and output access points. This makes it difficult to inject certain signals for normal ranges tests and robustness tests, and as well as verify/capture the results at the pin level.
How does Aldec help with this issue?
Since 2007, we have been providing a fully customized hardware and software solution that would enable our customers verify 100% of FPGA-level requirements in the target device using the HDL testbench as the test vectors. The HDL testbench typically verifies 100% of the FPGA-level requirements via simulations, and by using our solution, our customers are able to repeat the same test cases via physical tests in the target device. This helps them meet the verification objectives defined in DO- 254. Our customers who have successfully used this solution and achieved certification include Thales and Elbit Display Systems.
What is the most exciting opportunity for Aldec in the aviation market in the future?
Thanks a lot Louie for your time and I am really looking forward to seeing you face to face on DAC 2022.
Louie De Luna, Director of International Sales ALDEC, is responsible for FPGA level in-target testing technology and requirements lifecycle management for DO-254 and other safety-critical industry standards. He received his B.S. in Computer Engineering from University of Nevada in 2001. His practical engineering experience includes areas in Acceleration, Emulation, Co-Verification and Prototyping, and he has held a wide range of engineering positions that include FPGA Design Engineer, Applications Engineer, Product Manager and Project Manager.
Michael Geissel worked in various leading design application and marketing positions of internationally renowned companies before he welcomed eVision Systems. His many years of experience in ASIC and FPGA design, consulting and marketing ensure the customer-oriented orientation of the company. Michael Geissel is responsible for consulting, services and sales support for strategic customers.
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