The use of highly configurable IP-based designs has become the norm in the SoC era. Modern SoC designs targeting Xilinx® Zynq Ultrascale+ MPSoC include an extensive list of standard embedded IPs and custom IPs with memory-mapped registers. While these IPs vary in size and complexity, they are all configurable via registers that are typically composed of a field name, field width, access type, default values and policies. RTL simulations for verifying these IPs especially in various configurations require the use of hierarchical register models – creating them is not a trivial task and require a common framework and automation.
UVM provides a well-defined framework for modelling registers, commonly referred to as the Register Abstraction Layer (RAL). UVM RAL provides APIs to configure registers with various access policies including RW, RO, WO, W1S and RC. It also provides a set of handy pre-built sequences to automate certain common verification scenarios. A robust API on top of register model enables users to develop more automation on top of the built-in features.
In this webinar we will introduce UVM RAL and how the register models can be auto-generated in UVM from a standard IP-XACT format of CSV spreadsheet. We will also show how to use UVM RAL to model Zynq MPSoC registers.
- Zynq MPSoC design characteristics
- UVM RAL introduction
- Anatomy of UVM Register models
- Auto-generation of RAL models
- Adapter modeling in UVM RAL
- Using RAL to model Zynq MPSoC
- Details of Aldec solution
- Why UVM?
- UVM- Top-down and Bottom-up View
- UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
- Aldec solutions and live demo
- Using UVM for VHDL designs
- Port mapping rules and FPGA flow
- Binding SVA assertions to VHDL
- TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGA UVM for FPGAs Seminar Part 4 IEEE 1800.2 UVM Updates
- Anatomy of a typical UVM test bench
- UVM guideline class, copier, comparator, printer
- Case Study – Porting a VIP to IEEE 1800.2