The Accelera Universal Verification Methodology (UVM) became an IEEE standard published as IEEE 1800.2 – IEEE Standard for UVM Language Reference Manual (LRM). UVM has been the predominant verification methodology for ASIC designs for many years and has recently gained popularity and usage with FPGA designs.
UVM can improve interoperability and reduce the cost of reusing and integrating IPs. Think of lego-like verification process based on pre-built pieces/components/IPs – that’s precisely what UVM provides to design teams. Learning UVM can take a long time especially if one were to go by the extensive information provided in the LRM. In this webinar, we will cover the basics of UVM and how to get more productive with tips, tricks and techniques. We will walk through basic UVM features from a typical end-user perspective and learn to build a small testbench with UVM.
- What is UVM?
- Why UVM?
- UVM top-down and bottom-up view
- UVM macros – brief introduction
- VM transaction models
- UVM Driver
- UVM Monitor
- UVM Sequencer
- UVM Agent
- UVM Environment
- UVM Test
- UVM Sequences
- Details of Aldec solution
- Questions and answers
- Using UVM for VHDL designs
- Port mapping rules and FPGA flow
- Binding SVA assertions to VHDL
- TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
- Zynq MPSoC design characteristics
- Introduction to UVM RAL and anatomy of UVM register models
- Auto-generation of RAL models
- Adapter modeling in UVM RAL
UVM for FPGAs Seminar Part 4 IEEE 1800.2 UVM Updates
- Anatomy of a typical UVM test bench
- UVM guideline class, copier, comparator, printer
- Case Study – Porting a VIP to IEEE 1800.2