The requirements to increase the performance of the chips, but at the same time to reduce the power consumption, are often in conflict. At the same time, products with much more functions are to be brought to market at lower cost. The migration to ever-smaller structures puts extreme pressure on designers with ever more complex design rules and design options.
A complete schematic and analogue layout design process that combines flexibility, the latest design methodology and ease of learning without sacrificing important features for experienced users is becoming increasingly important. Also not to be overlooked is finding suitable business models for fast growing technology companies.