Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs.
To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals. Then a typical cycle related corner case is if you read/reset the counter in the same cycle as a new event occurs – risking strange behaviour in many ways. For this simple example, however, most designers will handle this correctly, – but for more complex samples – including something as simple as a UART, this type of corner case is highly error-prone.
This webinar will explain these corner cases in more detail and then show why they often result in bugs, why these bugs are often not detected, and how you can catch them.
- What is a cycle related corner case?
- Why is this problem?
- What does a typical error prone code look like?
- What is the probability of detecting or testing such a corner case?
- Why are the common solutions not working?
- Independent of tools, what is required to detect these corner cases?
- How can you use UVVM to detect these corner cases?
- Why UVM?
- UVM- Top-down and Bottom-up View
- UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
- Aldec solutions and live demo
- Using UVM for VHDL designs
- Port mapping rules and FPGA flow
- Binding SVA assertions to VHDL
- TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help
- Zynq MPSoC design characteristics
- Introduction to UVM RAL and anatomy of UVM register models
- Auto-generation of RAL models
- Adapter modeling in UVM RAL