IDesignSpec™ GDI

Next generation semiconductor automation

Agnisys IDesignSpec GDI (Graphical Design Interface) provides a complete solution for executable hierarchical specification of your memories, register sets, registers and register fields in an IP or SoC. You can choose from a variety of input formats. You can import existing descriptions in standard formats such as SystemRDL, IP-XACT, JSON, RALF, YAML, XML, and comma-separated values (CSV) files.

Powerful register and memory editor, SystemVerilog, UVM

IDesign Spec
You can specify the registers and memories using the templates and add-ins provided by Agnisys for Microsoft Word, Microsoft Excel or OpenOffice Calc.

For maximum utility and flexibility, you can choose the highly intuitive specialized register and memory editor included in IDesignSpec GDI, a graphical user interface (GUI) for entering specifications. IDesignSpec GDI interactively generates a variety of output files for the teams involved in your project, supporting design, verification, embedded programming, validation and documentation.

IDesignSpec GDI fits seamlessly into your SoC or IP development workflow, including integration with the Git revision control system to manage both text and graphics files and promote collaboration.

How IDesignSpec GDI improves your development process

These executable specifications, read by IDesignSpec GDI, support both simple registers and more than 400 special register types, including indirect, indexed, read/write-only, alias, lock, shadow, FIFO, buffer, interrupt, counter, paged, virtual, external, read/write pairs, and combinations of these types.

RTL generation of registers, memories, CDC logic and extended bus connectivity

IDesignSpec GDI interactively generates output files from your specifications for your design, verification, software and documentation teams. It generates the full RTL description for the registers and memories, including a bus slave and decode logic specific to the user-selected bus protocol, and clock-domain crossing (CDC) synchronization logic. This allows immediate connection of your design to the register bus. Supported interfaces include APB, AHB, AHB-Lite, AXI4, AXI4-Lite, TileLink, Avalon, Wishbone, and proprietary buses.

The generated SystemVerilog, Verilog, VHDL or SystemC RTL code for the registers is easy to read with easy to understand comments. Your hardware development team simply adds the generated files to its list of handwritten RTL blocks for application logic and third-party IP blocks for use with simulation, logic synthesis, and other tools in the development flow.

Generation of SystemVerilog testbench models and C/C++ headers

IDesignSpec GDI generates a SystemVerilog model that is compatible with the UVM standard and can be integrated into your UVM testbench. This saves your design and verification team a lot of work. IDesignSpec GDI also helps your embedded programmers by generating C/C++ headers for the memories, registers and fields. This replaces the tedious manual transcription of specification details into code and avoids the risk of errors during the process.

Generation of high-quality documentation from the specification

For your technical writers, IDesignSpec GDI generates high-quality documentation of registers and memories suitable for inclusion in user manuals. User-selectable formats include Microsoft Word, HTML, PDF, Markdown, and DITA.