UVM Register Model Generator, SystemRDL Compiler, IP-XACT Compiler

Agnisys IDesignSpec

IDesignSpec™ helps IP/SoC Design architects and engineers to create an executable specification for registers and automatically generate output for Software and Hardware teams. The exceptional innovation comes with an intuitive tool flow as the specifications can be written in MS Word, MS Excel, LibreOffice or text-based industry-standard formats such as SystemRDL, RALF or IP-XACT. IDesignSpec captures simple as well as special registers, signals, interrupts, and generates synthesizable RTL, UVM model, C/C++ Headers, HTML and PDF.

Register Design Entry

Equipped with user-friendly templates, you can specify your registers using any of the add-ins to Word, Excel, OpenOffice Calc or FrameMaker. Built with high-performance IP-XACT compiler and SystemRDL compiler, simple and complex registers can be created hierarchically such that large SoC designs are divided into manageable sub-blocks that are represented symbolically, designed and connected together. This methodology enables you to work on different parts of the de-sign in parallel with a large team. Users are able to convert register spec from IP-XACT to UVM or from SystemRDL to IP-XACT.

Code Generation

Based on the golden specification, various SoC teams can use the high-performance code generators via GUI or command line. The generated RTL Code (VHDL, Verilog, SystemVerilog or SystemC) for the registers is human-readable with easy-to-follow comments. The RTL also includes a bus slave and a decode logic specific to the bus protocol (AHB, APB, AXI, AXI-Lite, TileLink, or proprietary), ensuring instant connection of the application logic to the register bus. The UVM Register Model Generator generates a UVM verification model with Register Arrays, Memories, Indirect Access Registers, FIFO Registers and Coverage, Constraints Models and hdl_path. Users are able to customize various outputs by using our popular Velocity Template and TCL API, enabling you to meet various requirements for RTL, C++ Classes, verification code and documentation.

Special Registers

The UVM library includes examples of few commonly used special registers such as Indirect, Indexed, Alias and RO/WO Registers. But today’s SoCs demand more specialized register behaviour to meet various HW/SW interface requirements. IDesignSpec supports over 20 special registers including Shadow, Lock, Trigger-Buffer, Interrupt, Counter or External. CDC techniques are also supported for proper synchronization on both HW and SW interfaces.

Document Generation

The customizable Document Generator can output file formats such as HTML, PDF, Custom PDF, .doc, .xls, DITA, IP-XACT, SystemRDL or ARM CMSIS.

IDesignSpec™ – Key Features

Easy to use plugin for popular editors ensures a very rapid adoption rate

Powerful code generation keeps your specification synchronized with product development.

Imports : IP-xact, SystemRDL, XML, CSV, register data stored in native editor format. Provides complete register data portability with design teams and customers

Extensible: User defined transformations using Tcl or XSLT