HW-SW Codesign
When developing embedded systems applications, it is important to have a development process available for both system specification and verification that also considers the description and verification of the interface between HW and SW. For co-design and co-verification, our partners Agnisys and ALDEC offer the appropriate solutions.
HDL Design
Depending on the desired development process, editors integrated into the simulator, graphical editors or editing systems independent from the simulator can be used to create HDL code. With our partners Sigasi and ALDEC, we offer you the appropriate editor for your design flow.
HDL Verification
There are several tools available for the verification of HDL based designs. With the tools ALINT-Pro, Active-HDL and Riviera-Pro ( ALDEC), we offer static, structural and design rule-based checks and simulators for dynamic verification of VHDL Verilog, System-Verilog and SystemC.
Analog Verification
Extensive analog simulations quickly become a challenge with mixed-signal ASICs. Here it can be helpful not only to rely on CPU based technology but also on analog simulators, which offer significantly more performance than conventional CPU based systems by using GPUs. With ALPS and ALPS GT, our partner Empyrean Technologies offers powerful tools.
ASIC Layout
For creating complex layouts of ASICs, we offer a complete solution from our partner Empyrean Technologies.
