Still following Moore’s Law, more and more designs are migrating to new and smaller processes to offer products with new technologies demanded in mobile, networking, and automotive markets. There are huge challenges for analog simulation in these new processes in terms of capacity and accuracy. Post-layout simulation with an explosive number of extracted inductance and capacitance values lead to SPICE simulations that can take several days, weeks or even longer.
Combine this with the influences of voltage, temperature and process parameters, and the simulation requirements are extremely high, as insufficient accuracy is no longer acceptable. The potential risks to chip quality become high with verification strategies such as splitting circuits into small blocks and removing IOs and decaps. An extremely powerful, high-speed and accurate SPICE simulator is required.