Automatically generate UVM Sequences

Agnisys ISequenceSpec

A common Sequence specification serves as a powerful tool for stimulus generation used by multiple teams involved in verification, firmware and post-silicon validation stages. But most SoC teams lack a unified flow for creating sequences – each team has to manually write sequences in their formats, thus wasting time and resources.

ISequenceSpec™ enables users to describe the configuration, programming and test sequences of a device and automatically generate sequences that are ready to use during early verification stages, firmware development and post-silicon validation. From a single sequence specification, you can generate UVM sequences for verification, C code for firmware and device driver development, SystemVerilog sequences for validation, and various outputs, including CSV for Automatic Test Equipment.

Language Features and Properties

Sequences can be specified using a rich language and command feature set that includes loops, branch, wait, calls, switch, and macros. Several properties can also be defined for customizing the generated outputs. These properties can be created by using explicit property name-value pair or using the curly bracket syntax in the description.

Sequence Syntax Checker

Several semantic problems can occur during the development of a sequence. ISequenceSpec is equipped with a smart syntax and semantic checker for validating the format and syntax within the specification. The entire specification is validated, and a report containing a complete list of all problems opens in a window for viewing with cross-navigation to the row containing the problem. The checks carried out by the validation process include:

  • Register Validation – guides you to the row containing the register problem.
  • Syntax Validation – Sequence step validation is performed, which checks the existence

IDesignSpec™ – Key Features

  • Automate the generation of code for device initialization and other important device sequences
  • Simple, natural, portable sequence format for multiple IP/cores and SoC
  • Capture sequences at a higher level in-sync with register specification
  • Use register descriptions in standard formats like IP-XACT, SystemRDL, RALF or leverage on IDesignSpec™ integrated flow to use register data
  • Easy to use
  • Sequence constructs include loops, if-else, wait, arguments, constant, in-line functions etc.
  • Capability to compile, flatten and unroll the sequences
  • System Verilog UVM sequences for verification
  • Verilog for validation
  • Variety of formats for various Automatic Test Equipment
  • Documentation in HTML and other formats