Today’s FPGAs have become larger in logic density and can handle complex designs with multi-million system logic cells. The traditional verification techniques of simple simulations combined with a detailed validation in the lab simply do not scale up any longer. Even to map a large logic design to a modern-day FPGA takes many hours. FPGA verification is more and more moving towards simulation-based techniques and requiring more advanced verification capabilities such as those used in ASICs. In the field of ASIC design verification, UVM is the de-facto standard in developing testbenches, stimulus and coverage. While there is nothing ASIC-specific in UVM, the sheer complexity, transaction-level methodology and object-oriented approach keep many un-initiated FPGA designers away from adopting UVM.

In this webinar, we will share our experience in making UVM adoption easier for FPGAs. We will show how VHDL designs can use UVM testbenches with great ease. We will demonstrate how simple TCL based apps can help FPGA designers to quickly create a template for a given design. The availability of such apps will expedite UVM adoption in the FPGA community. We will also talk about certain unique challenges in FPGAs for space applications such as error injection testing and how UVM can be customized in solving some of these challenges.


  • FPGA evolution, complexity
  • Why UVM for FPGAs
  • UVM top-down and bottom-up view
  • Using UVM for VHDL designs
  • Port mapping rules
  • Binding SVA assertions to VHDL
  • TCL applications for automating the UVM skeleton in the FPGA flow
  • TCL apps to automate UVM skeleton in FPGA flow
  • Details of Aldec solution
  • Live-Demo

UVM for FPGA UVM for FPGAs Seminar Part 1 Get, Set, Go - Be Productive with UVM

  • Why UVM?
  • UVM- Top-down and Bottom-up View
  • UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
  • Aldec solutions and live demo

UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help

  • Zynq MPSoC design characteristics
  • Introduction to UVM RAL and anatomy of UVM register models
  • Auto-generation of RAL models
  • Adapter modeling in UVM RAL

UVM for FPGA UVM for FPGAs Seminar Part 4 IEEE 1800.2 UVM Updates

  • Anatomy of a typical UVM test bench
  • UVM guideline class, copier, comparator, printer
  • Case study – Porting a VIP to IEEE 1800.