There are several CI tools available such as Gitlab and Jenkins. In this webinar, we will be looking at these two tools and demonstrate how you can integrate Riviera-PRO into them – to run simulations every time there is a code change. We will walk through the various steps and scripts you will need to create to automate the process of CI. We will also look at how to generate and view coverage in these tools, plus we’ll show you how improvements can be made to the scripts to accelerate the simulations.
- Introduction to CI
- License and software requirements
- Steps to create the CI flow
Functional coverage is often mentioned together with constrained-random verification, which is a great combination.
How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
Cocotb, an approach to using Python as a testing language, allows developers to start with small, directed test benches and evolve them into more thorough constraint random tests.
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal...
Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.