AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses for dynamic verification. For the dynamic verification of AXI connections, Aldec offers FPGA manufacturer-independent AXI bus function models (BFM) and the Riviera-PRO functional verification platform.

In this webinar, we will present AXI bus interface extraction and static verification with ALINT-PRO. Then, we will show how ALINT-PRO assists in test harness wrapper generation for dynamic verification with Riviera-PRO. Finally, we will show the usage of Aldec AXI BFM solution for dynamic interconnect verification.

Agenda

  • Bus interfaces extraction
  • Bus interfaces static verification
  • Test harness development (script-based)
  • Aldec AXI BFM overview
  • Dynamic verification of AXI interconnect design using Aldec AXI BFM and Riviera-PRO
  • Live-Demo
  • Q&A

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