FPGA design and simulation
Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.
The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flow and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL supports industry leading FPGA devices from Intel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and more.
Top Features and Benefits
- Unified Team-based Design Management maintains uniformity across local or remote teams
- Configurable FPGA/EDA Flow Manager interfaces with 200+ vendors tools allows teams to remain on one platform throughout FPGA development
A typical FPGA design flow includes the design entry phase, synthesis, and implementation (fitting and Place & Route processing), each stage typically followed by simulation. Managing the project throughout the design flow along with the design data is becoming very important. The Design Flow Manager is the tool that is designed to automate these processes. It interfaces with third-party tools and provides FPGA designers with a unique platform that can be used throughout the FPGA design flow.
Benefits of using FPGA Project Management:
- It encloses the entire FPGA design flow from design entry to place and route which means that you don’t have to learn different vendor tools during different phase of FPGA design
- It interfaces with 90+ vendor tools which allows you to configure your flow in many different ways
- It collaborates with the version/revision control system to provide data and version management for your project
- Built-in Server Farm allows designers to manage the queue for their simulation, synthesis, and implementation tasks
Graphical/Text Design Entry
- Quickly deploy designs by using Text, Schematic and State Machine
- Distribute or deliver IPs using more secure and reliable Interoperable Encryption standard
Schematic / Block Diagram Editor
The Block Diagram Editor is a tool for graphical entry of VHDL, Verilog and EDIF designs. If your HDL design is in large part structural, it may be easier for you to enter its description graphically as a block diagram, rather than writing the source code. The Block Diagram Editor will then convert the diagram automatically into structural VHDL, Verilog or EDIF netlist. With Active-HDL, you can mix both types of description. For example, the top-level design entity can be a block diagram while the components instantiated in it are described using HDL code/EDIF netlist and/or state diagrams.
- The Schematic editor supports both bottom-up and top-down methodologies
- Schematic libraries for vendors allow you to create technology oriented block diagrams
- The Hierarchical property of editor helps you create multiple pages of the schematics for complex blocks
- Block diagram files can be translated to VHDL, Verilog or EDIF netlist
State Machine Editor
The State Diagram Editor is a tool designed for the graphical editing of state diagrams of synchronous and asynchronous machines. Drawing a state diagram is an alternative approach to the modelling of a sequential device. Instead of writing the HDL code by yourself, you can enter the description of a logic block as a graphical state diagram. The editor will then automatically generate the HDL code based on the entered graphical description. Due to the intuitive graphic form, state diagrams are easy to learn and far more readable than the HDL code.
Benefits of using State Machine Editor:
- It gives a visual map that specifies the flow, events and actions from state to state which is much easier to read and understand
- Built-in testbench generator can help verify your state machine very quickly
- It can be served as a great collaboration tool during design meetings as they are easy to understand and explain
- They can be used to document the design at various levels of abstraction
HDL Text Editor
The HDL Editor is a text editor designed for editing an HDL source code. It is tightly integrated with the compiler and simulator to enable debugging capabilities. Some of the major features of HDL text editor are Keyword highlighting (VHDL, Verilog/SystemVerilog, C/C++, SystemC, OVA, and PSL), Support for code groups and code structure, Auto-complete and Auto-format, Bookmarks and named bookmarks for easy navigation through source code, Breakpoints and Columns Selection.
Benefits of using HDL Text Editor:
- Cross probing between waveform viewer and HDL text editor makes debugging easier
- Signals can be add to waveform viewer directly from HDL Editor
- Supports live value probes in source code during simulation
- Language templates for VHDL, Verilog, SystemVerilog and SystemC to help write code quickly
Simulation and Debugging
- Powerful common kernel mixed language simulator that supports VHDL, Verilog, SystemVerilog and SystemC
- Ensure code quality and reliability using graphically interactive debugging and code quality tools
- Perform metrics-driven verification to identify unexercised parts of your design using Code Coverage analysis tools
- Improve verification quality and find more bugs using ABV – Assertion-Based Verification (SVA, PSL, OVA)
- Ability to simulate advanced verification constructs like SV Functional Coverage, Constrained Randomization and UVM
- Connect the gap between HDL simulation and high level mathematical modeling environment for DSP blocks using MATLAB®/Simulink® interface
SystemVerilog is a powerful IEEE approved language (IEEE 1800™) that enables significant improvements over its predecessor, Verilog HDL. This massive language combines many of the best features of VHDL, Verilog, and C++ and provides superior capabilities for system architecture, design, and verification.
SystemVerilog breaks down into three major areas: hardware description, assertions, and the testbench language Depending on the configuration of the tool and license configuration, designers can use features from these different areas of the language. SystemVerilog-based Universal Verification Methodology (UVM) is an industry-proven functional verification methodology approved by Accellera. Aldec provides a pre-compiled UVM library and SystemVerilog simulator to help customers meet the challenge of verifying today’s complex designs.
VHDL IEEE 1076-2008 language standard is a powerful, more user-friendly upgrade from previous versions. VHDL-2008 adds important language enhancements for verification and design engineers and delivers many benefits from numerous added functionalities, including: PSL incorporation (properties and assertions support), IP protection (encrypted files compilation), VHPI, fixed and floating point packages, generics packages, new types (integer_vector and boolean_vector, etc.), process for combinatorial logic, simplified conditional and case statements, extended assignments, new and enhanced operators, extended bit string literals, enhanced port maps, context declarations and clauses. VHDL IEEE 1076-2008 is the biggest VHDL language standard change since the VHDL IEEE 1076-1993.
Aldec includes support for VHDL-2008 in both Active-HDL™ and Riviera-PRO™ at no additional cost to customers with a valid maintenance contract and with a VHDL or mixed-language simulation configuration.
SystemC is an environment that allows the description and verification of digital systems using C++. Governed by IEEE 1666™-2005 and originally developed by the OSCI (Open SystemC Initiative). It is a library of classes and templates that provide hardware and system-related features not available in standard C++.
Both the Active-HDL and Riviera-PRO simulation and verification software solutions include support for C/C++ and SystemC and both offer designers seamless integration capability of HDL code and the various flavors of C. These IEEE-standardized interfaces allow simulation of HDL models with high-level C-based testbenches, instantiation of C models in HDL, connecting of custom visualization applications to HDL, performance of TLM and more.
The C/C++/SystemC environment is ready to use upon installation. The installer includes a supported C/C++ compiler, header files and library files required by various types of C applications (SystemC, SystemC+SCV, PLI, VHPI). C applications can be compiled with a dedicated command that sets the required defines, paths to header files, libraries to be linked, etc. This allows engineers to focus on development, rather than on the caveats of C++ compilers. A powerful set of debugging tools is also available with Aldec’s solutions.
Aldec simulators also contain a complete environment for developing and simulating SystemC Verification Library (SCV) applications. Recently popular SCV is built on the foundation of SystemC and Testbuilder, and it supports advanced randomization techniques, transaction recording, etc. Header files and pre-compiled library files are delivered alongside Aldec products.
- Abstract design intelligence and represent them in easy to understand graphical form using HDL to schematic converter
- Share designs quickly with auto-generate Design Documentation in HTML and PDF
A built-in documentation tool inside Active-HDL allows you to create a textual and graphical representation of your workspace or design in HTML or PDF. All design elements such as design files, waveforms, block diagrams and attached documents can be exported to HTML or PDF documents.
Benefits of using Documentation:
- It is extremely helpful for the processes such as design reviews, reuse and archiving
- The resulting documents always preserve the hierarchy of the design which provides easy navigation in complex designs
- Vector graphics images capability maintains the high resolution of schematic files in the generated document which makes it easy to read or print
- HTML format is supported in any web browser. And this way, designs/workspaces and their documentation may be shared among users who would like to analyze them without accessing Active-HDL
- HTML projects may be published in a local intranet network or Internet