AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA...
Aldec Event Articles
FPGA Design – Verification Code, Functional and Specification Coverage
FPGA Design/Verification Best Practices for Quality and Efficiency 19. May 3:00 PM - 4:00 PM Functional coverage is...
FPGA Verification Architecture Optimization with UVVM
FPGA Design/Verification Best Practices for Quality and Efficiency 5. May 3:00 PM - 4:00 PM For most FPGA projects,...
FPGA Design Architecture Optimization
PGA Design/Verification Best-Practices for Quality and Efficiency 28 April 3:00 PM - 4:00 PM The FPGA design...
Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for...
Increase your productivity with Continuous Integration flows
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a...
Constraint Random Verification with Python and Cocotb
Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean...
Using OVL for Assertion-Based Verification of Verilog and VHDL Designs
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular...
The most error prone FPGA corner cases
Presenter: Espen Tallaksen, CEO of EmLogicCycle related corner cases are probably the worst and main reason for...
UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates
Be productive with UVMStarted with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant...