Aldec Event Articles

FPGA Design – Verification Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, which is a great combination.

FPGA Verification Architecture Optimization with UVVM

How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.

FPGA Design Architecture Optimization

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...

FPGA Verification Architecture Optimization with UVVM

FPGA Verification Architecture Optimization with UVVM

Apr 7, 2022 | Aldec Event

FPGA Design/Verification Best Practices for Quality and Efficiency 5. May 3:00 PM - 4:00 PM For most FPGA projects,...

FPGA Design Architecture Optimization

FPGA Design Architecture Optimization

Apr 7, 2022 | Aldec Event

PGA Design/Verification Best-Practices for Quality and Efficiency 28 April 3:00 PM - 4:00 PM The FPGA design...

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Mar 8, 2022 | Aldec Event

Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for...

Increase your productivity with Continuous Integration flows

Increase your productivity with Continuous Integration flows

Jan 18, 2022 | Aldec Event

In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a...

Constraint Random Verification with Python and Cocotb

Constraint Random Verification with Python and Cocotb

Nov 4, 2021 | Aldec Event

Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean...

Using OVL for Assertion-Based Verification of Verilog and VHDL Designs

Using OVL for Assertion-Based Verification of Verilog and VHDL Designs

Oct 22, 2021 | Aldec Event

Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular...

The most error prone FPGA corner cases

The most error prone FPGA corner cases

Oct 22, 2021 | Aldec Event

Presenter: Espen Tallaksen, CEO of EmLogicCycle related corner cases are probably the worst and main reason for...

UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates

UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates

Oct 1, 2021 | Aldec Event

Be productive with UVMStarted with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant...