Aldec Event Articles

Essential steps to simplify VHDL testbenches with OSVVM

This Getting Started webinar focuses on the first, essential steps you need to take if you want to improve your VHDL testbench approach with OSVVM.

Checking AXI connections with ALINT-PRO and Riviera-PRO

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses...

FPGA Design – Verification Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, which is a great combination.

FPGA Verification Architecture Optimization with UVVM

How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.