AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA...

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA...
FPGA Design/Verification Best Practices for Quality and Efficiency 19. May 3:00 PM - 4:00 PM Functional coverage is...
FPGA Design/Verification Best Practices for Quality and Efficiency 5. May 3:00 PM - 4:00 PM For most FPGA projects,...
PGA Design/Verification Best-Practices for Quality and Efficiency 28 April 3:00 PM - 4:00 PM The FPGA design...
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for...
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a...
Testing digital hardware has never been an easy job, and it won’t get easier any time soon. But that doesn’t mean...
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular...
Presenter: Espen Tallaksen, CEO of EmLogicCycle related corner cases are probably the worst and main reason for...
Be productive with UVMStarted with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant...
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