Event Articles

FPGA Design – Verification Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, which is a great combination.

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FPGA Verification Architecture Optimization with UVVM

How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.

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FPGA Design Architecture Optimization

The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.

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Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
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