Event Articles

Essential steps to simplify VHDL testbenches with OSVVM

This Getting Started webinar focuses on the first, essential steps you need to take if you want to improve your VHDL testbench approach with OSVVM.

Checking AXI connections with ALINT-PRO and Riviera-PRO

AXI has become the most popular internal bus protocol with today’s FPGA and SoC FPGA designs. ALINT-PRO enables FPGA designers to extract, review and statically verify AXI bus interfaces. In addition, ALINT-PRO can assist with automatic generation of test harnesses...

embedded world 2025

From March 14 to 16, embedded world in Nuremberg will once again be open to visitors. At booth 4-548 of eVision Systems, we look forward to meeting everyone who wants to learn about our many new innovations!

FPGA Design – Verification Code, Functional and Specification Coverage

Functional coverage is often mentioned together with constrained-random verification, which is a great combination.

FPGA Verification Architecture Optimization with UVVM

FPGA Verification Architecture Optimization with UVVM

Apr 7, 2022 | Aldec Event

FPGA Design/Verification Best Practices for Quality and Efficiency 5. May 3:00 PM - 4:00 PM For most FPGA projects,...

FPGA Design Architecture Optimization

FPGA Design Architecture Optimization

Apr 7, 2022 | Aldec Event

PGA Design/Verification Best-Practices for Quality and Efficiency 28 April 3:00 PM - 4:00 PM The FPGA design...

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Using SVA for Requirements-Based Verification of Safety-Critical FPGA Designs

Mar 8, 2022 | Aldec Event

Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for...

The most error prone FPGA corner cases

The most error prone FPGA corner cases

Oct 22, 2021 | Aldec Event

Presenter: Espen Tallaksen, CEO of EmLogicCycle related corner cases are probably the worst and main reason for...

UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates

UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates

Oct 1, 2021 | Aldec Event

Be productive with UVMStarted with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant...

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