12. May 3:00 PM – 4:00 PM
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result, their products have significantly more undetected bugs. Randomization can be used in many ways, but it is of course, also important to know when not to use it.
This presentation will show several levels of applying randomization, both with respect to the actual DUT and the randomization functionality available. The main principles shown are tool independent, but the new UVVM randomization functionality will be used as examples, thus also giving you a kick start using this great tool.
- Where could randomization be applied?
- Directed vs Random
- Constrained Random
- Advanced Randomization using various approaches
- Optimized Randomization and how that works
- Various examples
- Great features to improve your testbench
UVVM, VVC-Framework Testbench Sequencer
Functional coverage is often mentioned together with constrained-random verification, which is a great combination.
How to make a simple, well-structured, and efficient testbench using the open-source Universal VHDL Verification Methodology (UVVM) architecture.
The FPGA design architecture is the single most important and primary factor in achieving development efficiency, quality, and reliability. The difference between a good and a bad design architecture can be about 50% of the workload.
Thursday 10. March from 3.00 pm to 4.00pm Requirements-based verification (RBV) is a popular verification process for FPGA designs used in safety-critical systems. The effectiveness of RBV is limited by the quality and precision of the requirements. Verification...
In a team environment, verification engineers push code changes every day, and sometimes several times a day, to a shared repository. Each change has the potential to introduce new bugs into the design. Accordingly, when many changes are being made, it is difficult to...
Cocotb, an approach to using Python as a testing language, allows developers to start with small, directed test benches and evolve them into more thorough constraint random tests.
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal...
Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.