12. May 3:00 PM – 4:00 PM
Randomization is very important for modern verification. Still, very few designers apply randomization sufficiently in their testbenches. This means they are missing out on a very important method for finding potential bugs in their design, and as a result, their products have significantly more undetected bugs. Randomization can be used in many ways, but it is of course, also important to know when not to use it.
This presentation will show several levels of applying randomization, both with respect to the actual DUT and the randomization functionality available. The main principles shown are tool independent, but the new UVVM randomization functionality will be used as examples, thus also giving you a kick start using this great tool.
Agenda
- Where could randomization be applied?
- Directed vs Random
- Constrained Random
- Advanced Randomization using various approaches
- Optimized Randomization and how that works
- Various examples
- Great features to improve your testbench
UVVM, VVC-Framework Testbench Sequencer
UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.