Methodology productivityHenderson, NV – November 16, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation...
Aldec Press Release Articles
Advancing VHDL’s Verification Capabilities with VHDL-2019 Protected Types
The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification.
Aldec Riviera-PRO™ UVM-Generator
Riviera-PRO™ has been enhanced with an automatic UVM generator function The addition promises to significantly increase the productivity of Riviera PRO users who take advantage of the Universal Verification Methodology, which provides guidance for creating and reusing verification testbenches.