Emulation & Prototyping
Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in developing complex FPGA, ASIC, SoC and embedded system designs. The quality of the products and the customer-oriented support particularly characterize Aldec. With an active user community of over 35,000, 50+ global partners, offices worldwide and a global sales distribution network in over 43 countries, the company has established itself as a proven leader within the verification design community.
Riviera-PRO™ has been enhanced with an automatic UVM generator function The addition promises to significantly increase the productivity of Riviera PRO users who take advantage of the Universal Verification Methodology, which provides guidance for creating and reusing verification testbenches.
Cocotb, an approach to using Python as a testing language, allows developers to start with small, directed test benches and evolve them into more thorough constraint random tests.
Open Verification Library (OVL) is a library of property checkers for digital circuit descriptions written in popular Hardware Description Languages and maintained by Accelera. The OVL checkers could be used not only in dynamic simulation, but also in formal...
Cycle related corner cases are probably the worst and main reason for undetected bugs on many FPGAs. To explain this in a simple way, – a cycle related corner case is for instance if you have an event counter where the number of counted events is critical and you read and reset this counter at regular intervals.
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.