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Active-HDL Desiger Edition Perpetual Lizenz

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FPGA design and simulation

Active-HDL™ is a Windows® based, integrated FPGA Design Creation and Simulation solution for team-based environments. Active-HDL’s Integrated Design Environment (IDE) includes a full HDL and graphical design tool suite and RTL/gate-level mixed-language simulator for rapid deployment and verification of FPGA designs.

The design flow manager evokes 200+ EDA and FPGA tools, during design entry, simulation, synthesis and implementation flow and allows teams to remain within one common platform during the entire FPGA development process. Active-HDL also supports Efinix’s FPGA devices

Top features and benefits of Active HDL Designer Edition


Perpetual Licence
A perpetual license is a license without an expiration date. A 1-year support contract is included with the purchase of a perpetual license.

Design input and documentation

HDL, text, block diagram and state machine editor
Mit Active-HDL können Sie verschiedene Arten von Beschreibungen mischen. Your design can contain textual HDL code as well as block diagrams and state diagrams.

Voice assistant with templates and autocomplete
The Voice Assistant is a tool that helps you develop HDL, Handel-C or SystemC source code and Aldec macro instructions.

Support for macros, Tcl/TK and Perl scripts
The Aldec simulators support various scripting methods that differ in their level of abstraction and their possible applications.

Project Management

Design Flow Manager for all FPGA manufacturers
The Design Flow Manager configures, controls and executes simulation, synthesis and implementation tools for all building blocks from Efinix, Altera®, Atmel®, Lattice®, Microsemi™ (Actel), Quicklogic®, Xilinx® and others in an integrated development environment.

Revision Management
Active-HDL has a powerful interface that enables communication and collaboration with several leading source revision control systems.

Team-based design management
Complex FPGA projects are often managed by different teams and require collaboration between team members. A powerful design management tool that allows teams to quickly collaborate on projects is therefore essential.

Workspace and draft archiving

To prevent accidental deletion of theme files and provide you with additional sharing and backup options, Active-HDL has a theme archiving feature that can archive the current theme or the entire workspace in a single ZIP file.

Supported standards

VHDL IEEE 1076 (1993, 2002, 2008 und 2019)
ALDEC simulators support the IEEE 1076-1993 standard, the IEEE 1076™-2002 VHDL standard, and most of the newly released IEEE 1076™-2008 standard.

Verilog® HDL IEEE 1364 (1995, 2001 und 2005)
ALDEC simulators provide full support of the IEEE 1364-2005 standard. To enable the simulation of a variety of Verilog designs, both old and new, ALDEC simulators can be set to operate in Verilog ’95, 2001, and 2005 modes. More

SystemVerilog IEEE 1800 – 2012 ( Design)
SystemVerilog is a set of extensions to Verilog HDL that enable higher levels of modeling and efficient verification of large digital systems. More

Verification libraries (OSVVM, UVVM, cocotb)

Troubleshooting and analysis

Hierarchy viewer with configuration support
The Design Hierarchy Viewer is a tool that allows designers to view the project structure without elaborating it.

Interactive code execution monitoring
Stepping through source code is one of the most common debugging methods. Stepping involves executing the code line by line

Modern breakpoint management
Simulations can be stopped at a breakpoint. Aldec supports both source code breakpoints and signal breakpoints.

Signal probes on graphics/animation of graphics
Aldec simulators can maintain communication with graphical design sources during simulation and transfer live values of ports and signals to the block diagram editor, where they can be displayed in the form of colored probes.

Memory Viewer
The Memory Viewer is a debugging tool for viewing memory objects defined in an active theme.

FSM toolbox
Active-HDL provides features to help the user debug their bubble charts, including object sorter, chart report, trace over transition, current state highlighting, etc.

Accelerated Waveform Viewer (ASDB)
The Accelerated Waveform Viewer is a high-performance tool for graphically displaying simulation data stored in a binary simulation database (*.asdb).

Multiple waveform windows
For large designs where multiple signals need to be observed during simulation, it is impractical to keep them in one waveform window: since not all signals fit in one window, frequent scrolling is required to reach the desired waveform data.

Waveform stimulator
When a quick review of some parts of a large design is required, creating a testbench is not economical: testbenches work best when complete designs are tested in multiple simulation runs.


Performance of the simulation
Active-HDL includes simulation optimization features for both VHDL and Verilog that speed up simulation and significantly reduce simulation time.

Support for mixed language themes

Verilog programming language interface (PLI/VPI)
The Verilog PLI (Programming Language Interface) and VPI (Verilog Procedural Interface) provide a standard mechanism for accessing and modifying data in a simulated Verilog model.

Protection of simulation models
Library protection provides four levels of security when distributed models in the form of library files without releasing their source code.

Verilog® IEEE 1364™-2005 encryption
Using standard design source encryption is a much simpler form of managing IP creation and delivery than any type of binary file encryption. Riviera-PRO supports the standard methodology introduced in IEEE Std. 1364-2005.

VHDL IEEE 1076™-2008 encryption
Using standard design source encryption is a much simpler form of managing IP creation and delivery than any form of binary file encryption. Riviera-PRO supports the standard methodology introduced in IEEE Std. 1076-2008

IEEE 1735™ interoperable encryption

Support Value Change Dump (VCD and Extended VCD)
The VCD (Value Change Dump) file format is specified in the IEEE Std. 1364-1995 standard. The VCD file is an ASCII file that contains header information, variable definitions and variable value changes.

Precompiled FPGA vendor libraries

Xilinx® ISE SecureIP support

The simulator can operate with 64-bit bus throughput and utilize expanded memory.

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* Offer is valid for all Efinix customers in Germany, Austria and Switzerland