Automation of IP and SoC development
Agnisyshas expanded its original focus on register automation to encompass specification-driven design, verification, embedded programming, validation, and documentation of IPs and SoCs This expansion is a testament to Agnisys growth and the many challenges semiconductor development teams face. Sheer complexity is the most apparent issue; today’s designs contain billions of gates with thousands of blocks and countless interconnections.
It’s impossible to develop a chip this large without effective reuse. This happens across the industry via standards, across projects using design and verification IP, and across levels, from block to subsystem to complete SoC. Of course, there is also new design content in every chip, and hand-writing all the design, verification, and software takes precious time and consumes valuable resources. Tight project schedules demand that code generation be automated wherever possible, minimising manual coding errors and improving code quality.
The challenges are more significant in an SoC than a traditional chip because of the combination of hardware and software. The design blocks must be appropriately integrated, the embedded software controlling these blocks must be merged, and the entire hardware-software system must be validated together. More engineers are involved: architecture, hardware design, verification, embedded programming, and system validation teams. A typical specification is essential to keep these teams aligned, but that’s easier said than done. There is no standard way to capture specifications, with different groups using different methods Most use natural language, which is inherently ambiguous and subject to differing interpretations
Even if a perfect specification somehow exists, change is the only certainty Issues discovered during implementation and responses to competitive pressures require modifications to every specification many times on every project. Whenever this happens, it causes a waterfall effect. Changes to the hardware design are almost always necessary, mandating re-verification In many cases, software revisions are also required, demanding re-validation. End-user documentation must be aligned with the changed specification. If all the updates for the design, verification environment, embedded code, and documentation are made manually, many times per project, the impact is enormous.
Specification-driven automation is the only viable solution. Whenever possible, specifications must be captured in an executable format and used to automatically generate code and documentation for all stages in the development process. This is where Agnisys comes in. Agnisys provide a wide range of products that support many specification forms, check for correctness, and perform the generation steps. As shown in the diagram below, this process benefits multiple teams on the IP or SoC project.
This process has four primary specification inputs:
Specification for registers and memory
The specification for registers and memories is used to generate design RTL code, UVM testbench models and sequences for verification, C/C++ code for drivers and embedded software, and user documentation
Standard IP blocks
For standard IP blocks, the library generates all the same outputs.
For non-standard blocks, the specification for custom sequences generates UVM sequences, C/C++ code, and documentation.
Chip hookup specification
For SoC-level connection of IP and custom blocks, the chip hookup specification generates the top-level RTL design and documentation
This process benefits five primary project teams:
- The hardware designers use the generated RTL code as part of their designs
- The verification team incorporates the generated UVM models and sequences into their test benches and may also run the generated C/C++ code for initial validation
- The embedded programmers include the generated C/C++ code in their drivers and other software that communicates directly with the hardware
- The bring-up teamruns the drivers and embedded code in the lab as part of full-system hardware-software validation
- The technical writers incorporate the generated documentation into their user manuals
Because of the frequent changes in specifications, this process saves time and resources many times over the project, not just once. It eliminates hand-coding, tedious manual updates, introduced errors, and the verification effort to find and fix them. Agnisys automates hardware design, software coding, verification, validation, and documentation for many parts of IP and SoC development. To learn more about how this process works, including which products handle which aspects of the flow, please watch the Agnisys DVCon introductory video.
Requirements for various project teams and various tasks in the System-on-Chip (SoC) development process: hardware design, simulation, formal verification, firmware coding, system-level validation, and more.
The Standard Library of IP Generators (SLIP-G™) has proven to be very popular with users, and this is not surprising. Reuse plays a significant role in system-on-chip (SoC) development.
This post focuses on the UVM Register Abstraction Layer (RAL), sometimes called the UVM Register Layer. Today’s large system-on-chip (SoC) designs contain many control and status registers, often accessible from embedded software or drivers as well as hardware.
Agnisys has developed a unique approach that uses artificial intelligence (AI) and machine learning (ML) to translate English descriptions of design intent into SystemVerilog Assertions (SVA).