Many great ideas for best practices, new features and even completely new tools come from your users. They are all part of the Agnisys development process. As part of the close collaboration, users often evaluate new features before release, and even earlier in the process, they validate prototype technologies.
Agnisys has developed a unique approach that uses artificial intelligence (AI) and machine learning (ML) to translate English descriptions of design intent into SystemVerilog Assertions (SVA). This application has the potential to revolutionise the use of assertions without the need to learn the details of SVA.
Like any AI/ML application, this technology relies on training to learn and get better over time. Agnisys has already provided countless examples, including from industry experts, and now Agnisys is asking for your help. There are many ways to express design intent in natural language. We, therefore, invite you to visit https://www.ispec.ai/, enter your own English text and check the SVA generated by Agnisys. This technology is still under development, so you will probably find that some of your descriptions do not generate a perfect SVA. You can simply click a button to provide feedback.
Agnisys has also developed the ability to translate SVA into English descriptions, which will be very valuable for checking SVA, understanding assertions in IP blocks and inherited code, and documenting all assertions. We also invite you to include some interesting SVA examples and review the generated description. Here you can also easily give feedback.
It’s a lot of fun to experiment on the website. This is your chance to play with AI/ML and help Agnisys improve a promising new technology, so have fun!