The Standard Library of IP Generators (SLIP-G™) has proven to be very popular with users, and this is not surprising....
Agnisys Blog Articles
Automating the UVM Register Abstraction Layer (RAL)
It’s hard to think of any electronic design automation (EDA) innovation that’s had more impact than the Universal...
Automation of IP and SoC development
Agnisyshas expanded its original focus on register automation to encompass specification-driven design, verification,...
Specification Automation for Designers
Requirements for various project teams and various tasks in the System-on-Chip (SoC) development process: hardware design, simulation, formal verification, firmware coding, system-level validation, and more.
A high quality standard for standards-based IP
The Standard Library of IP Generators (SLIP-G™) has proven to be very popular with users, and this is not surprising. Reuse plays a significant role in system-on-chip (SoC) development.
Automating the UVM Register Abstraction Layer (RAL)
This post focuses on the UVM Register Abstraction Layer (RAL), sometimes called the UVM Register Layer. Today’s large system-on-chip (SoC) designs contain many control and status registers, often accessible from embedded software or drivers as well as hardware.
Automation of IP and SoC development
Agnisys has expanded its original focus on register automation to encompass specification-driven design, verification, embedded programming, validation, and documentation of IPs and SoCs This expansion is a testament to Agnisys growth and the many challenges semiconductor development teams face.
Automatically translate English description into SystemVerilog Assertions
Agnisys has developed a unique approach that uses artificial intelligence (AI) and machine learning (ML) to translate English descriptions of design intent into SystemVerilog Assertions (SVA).