The 10 biggest problems with the development using the I3C bus system

Developers of end devices and embedded systems, especially for use in IoT (Internet of Things), automotive and industrial automation, are faced with ever-increasing demands for low power consumption, data bandwidth, and miniaturization. To meet them, the embedded control and command interfaces such as MIPI I3C play an important role. Since the previous interfaces, such as I2C, SPI, and CAN, often no longer meet the requirements, a transition to newer interfaces, such as I3C (Improved Inter-Integrated Circuit, also known as SenseWire), is necessary.

 

What are the problems and challenges in implementing the I3C Basic or I3C specification, and what solutions are offered?

q

1. continuous data traffic on the I3C bus has to be monitored.

Prodigy Technovations’ PGY-I3C-EX-PD can simultaneously generate I3C traffic and decode and store the protocol of the bus.

q

2. Support of all existing I2C devices

The PGY-I3C-EX-PD supports the I2C protocol and can generate a 50ns clock high time during the emulation of the I2C traffic. This allows you to test the spike filter on the I2C slave devices.
.

q

3. Possibility to display timing variations

The timing and plot diagrams of the I3C Protocol Analyzer help the user to identify timing problems. This allows developers to fine-tune designs to meet I3C timing specifications.

q

4. Support for full-speed topology

The PGY-I3C-EX-PD supports SCL frequencies from 1Hz-12.5MHz (SCL is the “Serial Clock” signal for data transfer)

.

q

5. Protocol and error analysis of I3C bus messages on the I3C bus.

The I3C Analyzer in the PGY-I3C-EX-PD I3C Protocol Analyzer continuously monitors the communication on the I3C bus. The decoded results are displayed in the log list and time window, and the software summarizes the various log errors in the results and displays them to the user.

q

6. Display or capture of a specific defined event

The PGY-I3C-EX-PD from Prodigy Technovations supports powerful multi-level trigger functions. This allows design and test engineers to capture log activity on specific events and analyze elusive problems on the I3C bus.

.

q

7. You need to record data over a longer period for error analysis

The PGY-I3C-EX-PD supports continuous streaming of protocol activity to the host computer. This allows I3C protocol traffic to be captured on the I3C bus with nearly several gigabytes of memory buffer (theoretically limited only by the host computer’s memory space).

q

8. Emulation of the I3C bus configuration

In practice, I3C devices are expected to operate in an I3C bus configuration. There is a main master, a secondary master, and several I3C slaves. Therefore, the development and test engineer must test the I3C devices in the I3C bus configuration. PGY-I3C-EX-PD can be configured as a single master and 3 slaves. Users can set up the various characteristic registers of the I3C devices in PGY-I3C-EX-PD and configure the I3C bus together with the DUT.

q

9. Check I3C designs for MIPI conformance issues.

Early in the design cycle, interoperability testing is essential to shorten time-to-market and ensure seamless functionality between different devices from a wide range of vendors in the field. For this reason, the PGY-I3C-EX-PD supports the defined MIPI standard Conformance Test with the Conformance Test Suite (CTS v1.1).

q

10. Support of future I3C releases

I3C is constantly being further developed. Therefore, it is always important that the latest functionalities and definitions are taken into account. The PGY-I3C-EX-PD firmware is upgradeable to support future versions of I3C.

Prodigy I3C Protocol Analyzer and Exerciser

The PGY-I3C-EX-PD is the leading instrument that allows development and test engineers to test I3C designs to their specifications by configuring the PGY-I3C-EX-PD as a master/slave to generate I3C traffic with error injection functions and decode I3C protocol packets.

I3C Protocol Analyzer and Exerciser Prodigy

About I3C

MIPI I3C is an intelligent and highly scalable command, control, and data interface for connecting peripherals (sensors, accelerometers, gyroscopes, touchscreens, and more) to an application processor, providing developers with numerous opportunities to create innovative designs for a range of products – including PCs, wearables, IoT products, smartphones, automotive systems, and more.
I3C is considered the successor to I2C, yet I3C incorporates vital attributes of the traditional I2C and SPI interfaces to provide a very low-power, high-performance solution with backward compatibility and a flexible and secure upgrade path.

The 10 biggest problems with the development using the I3C bus system

Developers of end devices and embedded systems, especially for use in IoT (Internet of Things), automotive and industrial automation, are faced with ever-increasing demands for low power consumption, data bandwidth, and miniaturization. To meet them, the embedded...

Protocol Analysis and Debug

Seminar agenda: QSPI protocol basics, overview of the QSPI protocol, vulnerabilities and challenges of QSPI protocol analysis, capturing the QSPI protocol and analysis, live product demo.

Industry’s first electrical AC DC validation solution for SD cards and eMMC devices

PGY-SSM-EV-TesterForstinning (Germany), November 23, 2022 - eVision Systems GmbH, authorized Prodigy Technovations distributor for Central Europe, announced its PGY-SSM-EV-Tester SD, eMMC AC/DC Electrical Validation Tester for electrical characterization of SD card...

eVision Systems GmbH announces innovative PCIeGen3 and 4 protocol analyzer from Prodigy Technovations

PGY-PCIeGen3/4-PA PCIe Protocol AnalyzerForstinning (Germany), October 09, 2022 - eVision Systems GmbH, the authorized distributor of Prodigy Technovations for Central Europe, announces the PGY-PCIeGen3/4-PA PCIe Protocol Analyzer, the 2.5, 5.0. 8.0 and 16GT/S speeds...

UFS 4.0 Protocol Analysis and Validation Webinar

Validation and debugging of the UFS4.0 protocol with the MPHY HSG5B specification of 23.2 Gbps data rate and low power consumption is challenging due to the signal characteristics of the PHY layer and the data rate