Agnisys SoC Enterprise™
SoC Enterprise™ provides a flexible and customizable environment for SoC design assembly to comprehensively meet specific design requirements. It’s not just an assembler as it can also generate RTL components like bus-aggregators, bridges (AHB-APB, AXI-APB, AXI4Full-AHBFull), muxes and other “plumbing” components by leveraging already existing and mature register solution along with the new “Standard Library of customizable & configurable IP Generators” (SLIP-G™).
After generating blocks with registers through IDesignSpec™, our customers can stitch them together into an SoC and package them with SoC Enterprise.
SoC-E supports IPs from different sources and formats as below:
- IPs created by user manually
- IPs generated by SLIP-G
- RTL/IP-XACT generated from specifications using IDesignSpec™
- Third party IPs in RTL/IP-XACT format
It provides the following benefits:
- Automated, repeatable process that saves time and creates “correct-by-construction” outputs
- Eliminate manual coding errors in IPs and connecting RTL
- An intuitive graphical view of blocks and their connectivity with facility to traverse the hierarchy helps visualize the SoC
Flow from specification to SoC is as depicted below: