Thursday, October 7, 2021 3:00 PM – 4:00 PM CEST

Started with an early adaptor release as Accellera 1.0a, UVM has evolved into few significant versions including UVM 1.1 and UVM 1.2. As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.

UVM is currently the most adopted industry standard in VLSI/Semiconductor design world. With decades of proven Best Known Methods (BKMs), UVM brings productivity to every team in short span of time. In this webinar, we will walk through UVM evolution over a decade in Accellera and then in IEEE since 2017 Some of the changes are backwards incompatible and needs attention from users while migrating.

Agenda:

  • UVM evolution
  • Anatomy of a typical UVM test bench
  • UVM Policy class
  • UVM copier
  • UVM comparer
  • UVM printer
  • UVM factory changes
  • UVM component updates
  • UVM Reg unlock feature
  • Case study – porting a VIP to IEEE 1800.2
  • Details of Aldec solution
  • Live-Demo
UVM for FPGA

UVM for FPGAs Seminar Part 1 Get, Set, Go - Being Productive with UVM

  • Why UVM?
  • UVM- Top-down and Bottom-up View
  • UVM-Makros, Transaktionsmodelle, Treiber, Sequencer, Agent, Env, Test, Sequenzen
  • Aldec solutions and live demo
UVM for FPGA

UVM for FPGAs Seminar Part 2 Solving FPGA Verification Problems with UVM

  • Using UVM for VHDL designs
  • Port mapping rules and FPGA flow
  • Binding SVA assertions to VHDL
  • TCL applications for automating the UVM skeleton in the FPGA flow
UVM for FPGA

UVM for FPGAs Seminar Part 3 Verify Zynq MPSoC Designs? Learn how UVM Register Access Layer (RAL) can help

  • Zynq MPSoC design characteristics
  • Introduction to UVM RAL and anatomy of UVM register models
  • Auto-generation of RAL models
  • Adapter modeling in UVM RAL