Aldec at DVCon Europe: Aldec demonstrates a hybrid co-verification platform for ASIC/SoC projects and automated FPGA partitioning software
eVision Systems GmbH, Forstinning, Germany – October 18, 2019 – Aldec, Inc. a leading provider of mixed HDL speech simulation and hardware-assisted verification for ASIC and FPGA design, will exhibit at DVCon Europe (October 29-30, Munich, Germany), showcasing a powerful hybrid co-emulation platform for large-scale ASIC and SOC designs.
The platform was created incorporating an Aldec HES-US-440 hardware emulation system and an Aldec TySOM-3 embedded system board, offering a Xilinx Zynq® Ultrascale+TM FPGA that includes a quad-core ARM® Cortex-A53. An FMC Host2Host bridge between the two Aldec products enables the ARM cores to be shared with HES (hardware embedded simulation) using the TySOM board, allowing software team members to prototype fast clock speed hardware benefit from rapid system startup (minutes rather than hours).
Aldec will also demonstrate the recently introduced automatic FPGA partitioning feature of its popular HES-DVMTM tool, its fully automated and scalable hybrid verification environment for SoC and ASIC designs. Typically, and depending on the complexity and constraints of a design, manually partitioning multiple FPGAs for prototyping can take days or even weeks. In contrast, HES- DVM can complete the task in minutes.
“We will be showcasing solutions at DVCon Europe that exemplify what Electronic Design Automation (EDA) is all about: saving a tremendous amount of development time and improving safety in verification through automation,” commented Krzysztof (Chris) Szczur, an Aldec Hardware Verification Products Manager, who will be at DVCon Europe on both days at booth #405.
In addition, Aldec will use DVCon Europe to showcase the latest feature in Active-HDL, the Windows®-based integrated creation and simulation solution for FPGA design that provides a fully integrated HDL development environment consisting of text-based and graphical input that is seamlessly integrated with the simulator and supports all RTL and gate-level languages.
Aldec will also preview numerous features planned for integration into the next version of Riviera-PROTM, the company’s well-known verification platform that provides support for the latest verification libraries (e.g., from UVM), as well as simulation optimization algorithms to achieve optimal performance in VHDL, Verilog, SystemVerilog, SystemC and mixed-language simulations.
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