Agnisys at DVCon Europe: Unveiling test sequence generator for RISC-V cores and SoCs

Munich, Germany – October 21, 2019 – Agnisys, Inc.a leading EDA provider of the industry’s most comprehensive hardware/software interface (HSI) design and verification solution for System on Chip (SoC) designs, will showcase a novel test sequence generator for RISC-V cores and SoCs at DVCon Europe in Munich, October 29-30, 2019.

“One of the biggest challenges in creating test sequences is that the same sequence functionality needs to be coded multiple times in UVM, C or CSV by multiple engineers to support different test environments,” said Anupam Bakshi, founder/CEO. “This aspect of verification can certainly be automated to increase the productivity of development teams.”

Using the Golden Spec methodology, ISequenceSpec™ provides the environment for describing test sequences in pseudocode using Python text, Word™ document or Excel™ spreadsheet. The sequence generator can adapt the sequences in different languages such as SystemVerilog UVM for simulation, C/Python for firmware testing and Python/C/ASCII/CSV for board testing.

We invite you to see our demo at booth #301. The demo is based on a SweRV™ core, a 32-bit dual-issue 9-stage pipelined open-source processor. We have described the initialization and regular operation of the on-chip programmable interrupt controller. The automatically generated sequences include the following:

UVM sequence package for UVM-based simulation.
We create sequence classes that are extended by ‘uvm_reg_sequence’. Arguments are thereby processed via the ‘init” function. Read/write transactions on registers via the register model ‘rm’ within the task body.
• – sequence file
• – package file

C sequence package for firmware tests
We create functions with a specific ‘return type’ that can be changed in the configuration settings. Users can perform register and field writes via the tool’s default APIs or custom APIs.
• h – header file
• c – sequence file
• h – API file
• h – package file

Platform sequence package for testing boards.
Users can specify the base address of the IP address implemented on the board, create APIs to write/read the registers, and predefine initialization and cleanup functions. After generation, the sequences are ready to run on the board.
• h – header file
• c – sequence file

Prices and availability

Information on prices and availability is available at this contact:

Press contact:

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Josef Ostermeier
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