In this webinar, we will introduce transaction-level methodology (TLM), and how it can be used for verifying PCIe-based FPGA designs for DO-254 compliance. Transactions are easier to manage and correlate with the simulation results, therefore traceability is much easier to establish. Also, the untimed testbenches used with TLM are not sensitive to clock frequency and phase changes, which is ideal for verifying PCIe-based FPGA designs with non-deterministic behavior.
We will also show a complete flow using TLM from simulation all the way to target FPGA physical testing with our popular CTS platform.
Agenda:
- Typical architecture of PCIe-based FPGA design
- Verification challenges
- Introduction of TLM
- Differences between bit-level and transaction-level
- Benefits of TLM
- Simulation + target FPGA physical test using TLM
- Q&A
UVM for FPGAs Seminar – Part 4 – IEEE 1800.2 UVM Updates
As with many popular useful standards, UVM has attained the coveted IEEE standardization in 2017. Interestingly, UVM is the first verification methodology to be standardized, and the current version is IEEE 1800.2-2020.