VHDL Basic

This training will take 2 day long. Basic Knowledge is not required.

The VHDL basic course is targeting designers with basic knowledge about the development of digital circuits. The attendee will learn during the 2 days how to implement elementary circuits in an FPGA using VHDL language.
Beside the basic constructs of VHDL, the basic elements of an FPGA flow with design entry, simulation, synthesis and mapping (example is the Lattice flow) will be processed.

In practical exercises the attendee gets the opportunity to describe the essential elements of digital design (for example counters, simple state diagrams, combinational logic) using the VHDL language and practice the FPGA design with simple examples.

Dates and Prices

Our regular training dates that are listed on the German page are teached in German language only. Nevertheless we offer all trainings in English on demand. English based trainings can be offered in our regular training center or on side.

For questions about prices, locations and dates please contact us per email .