PCI-Express IP Core

The 2 day course targets designers, who wants to transfer projects from PCI to PCI Express with help of the Lattice IP Cores or designers, who wants to get introduced to subject of PCI Express. The training covers the substantial design aspects in regards of the design of a Lattice ECP2/M FPGA with a PCI Express interface.

In the first part of the course we explain the most important differences between the existing PCI and the PCI Express bus. Afterwards we will go into the specifics of the PCI Express bus in conjunction with the hardware development.

Following topics will be addressed:

Transaction Layer:

• Description of the different kinds of TL-packages
• Credit Based Flow Control
• Qualtity of service in connection with traffic classes and virtual channels
• Interrupts

Data Link Layer:

• Power Management in PCI Express

Physical Layer:

• Construction and function of the link training and status state machine

Subsequent an functioning PCI Express system will be build based on the Lattice PCI Express X 1 core within a mixed language simulation environment. The main attention is on the integration of the Lattice core. Based on the description of the various features of the PCI Express core the whole design flow will be represented.

As special gift we included a CD with a comprehensive PCI Express transaction environment. You can save money for expensive verification tools while you use the environmenr for a successful implementation of your Lattice ECP2/M project.

Pre-Condition:
We recommend the VHDL basic course as pre-condition for these training

Dates and Prices

Our regular training dates that are listed on the German page are teached in German language only. Nevertheless we offer all trainings in English on demand. English based trainings can be offered in our regular training center or on side.

For questions about prices, locations and dates please contact us per email .