Integrated FPGA Design & Verification

Aldec Active-HDL

Active-HDL is a comprehensive and complete design environment for FPGA design and verification using VHDL, Verilog and C/C++. Engineers and design teams are getting a powerful FPGA vendor independent tool for circuit design and verification. Active-HDL is a state of the art simulator used nearly in all markets and for all applications. Substantial customer feedback helps to increase constantly the design productivity and the ease of use.

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Target usage

Often we are asked which Active-HDL configuration would have the best price/performance for the target application. Upon completion of a survey and based on our experience we recommend the followings.

Classes of customers using Active-HDL configurations:

• Active-HDL Designer Edition for customers developing once a while small or mid size complex FPGAs (about 30 – 50 man days per year).
• Active-HDL PLus Edition for customers regularly developing small and mid size complex FPGAs or utilizing complex IP cores like PCI Express (50 – 120 man days per year). Depending on the IP used mixed language support (VHDL & Verilog) may be required.
• Active-HDL Expert Edition for customers using their majority of time to design complex or high complex FPGA using VHDL and/or Verilog (more than 120, man days per year).

Advantage of the commercial tool compared to the OEM version provided by the FPGA vendor.

Local support from eVision Systems and Aldec:

• FPGA independent design flow (all common FPGA design flows are supported within one tool).
• Text and graphical entry for Block und FSM.
• Faster simulation (Design Edition factor 2x, PE Version, factor 6 and EE version Faktor 9).
• The perpetual licenses can be expanded to capabilities like Code Coverage, Linting, PSl…).

All of these advantages will lead to an efficient development process and helps to implement your design into a FPGA, more quickly and with less risk.

Datasheet, software download and a feature comparison sheet of the different configurations are available as well as additional technical information below.

Active-HDL Movies
Product Trainings
Technical Documents

In August 2010 Aldec annouced the new version of Active HDL 8.3. Here you will find the News

Top Features

• Multi-FPGA & EDA Tool Design Flow Manager
• Graphical Design entry & editing
• Code2Graphics and Graphics2Code
• Import/Export Legacy Designs
• Pre-compiled FPGA vendor libraries
• High Performance Mixed-Language RTL Simulator
• IEEE Language Support: VHDL, Verilog®, SystemVerilog Design, SystemC
• Automatic Testbench Generation
• Advanced Debugging & Code Coverage
• IP Encryption and Xilinx® Secure IP support
• ABV, Assertion-Based Verification (SVA, PSL, OVA)
• DSP Co-simulation with MATLAB®/Simulink®
• PCB Design Interface
• Server Farm Manager
• HTML and PDF Design Documentation

Hersteller-unabhängiger Design Flow in Active HDL

Aldec Webinars

Applications engineers present continuously in live presentation and product demonstrations solutions for current design and verification problems.

Date, topics and content of the events here