HDL Synthesis

Synthesis: From RTL level to technology mapping

Synthesis tools enables the automated crossing from RTL abstraction level to the technology level. In VHDL an adder is described with a few line of code, while the description on technology level is the connection of many single logic elements and silicon matched macro cells. Synthesis is an automatic process translating HDL Code into a technology depended ( the target technology has to be defined) netlist used for the ASIC manufacturing process or for the programming of the FPGA.

Synthesis tools are offered by EDA vendors, especially for chip and complex FPGA designs or by the FPGA vendors. The synthesis tools in the vendor flow typically are low cost versions with a limited features set dedicated to the target FPGA technology. The Lattice ispLever flow for example includes the leading Synthesis tools Synplify and Synplify Pro from Synopsys.