HDL Simulation

Functional model simulation

The VHDL or Verilog description of a circuit is not a program with classical meaning, it is considered as a model. It should represent the behavior of the module under design on RTL level . As soon a module is described it should be verified that the models behave matches the desired behave of the circuit. The complexity of todays FPGA and ASIC designs makes the verification to a necessity because it is hardly controllable to find failures in the completed system.

While the HDL Code checking deals with inspection of formal code style requirements, the simulation takes care to test the implemented functions of the target system. Normally it is differentiated between a model of the system environment ( test bench) and the FPGA or ASIC model ( design under test) which has to be implemented.
The test bench in simulation is used to generate appropriate stimuli for the design under test (dut) and helps eventually to interpret automatically the simulation results. During simulation the stimuli will be applied to the HDL model and the results will be recorded. After simulation is finished the results will be analyzed manually or automated. The analysis can be made on text based stimuli files or waveform diagrams.

Also the development of a comprehensive test environment for the HDL means an additional effort, this step has an essential impact to the quality and efficiency of the design process. “Try on Error” approaches might work for small PLD designs but for sure is not usable for complex designs.
Design entry and simulation takes depend on the complexity of the project up to 70% of the total project time. Because the goal is to simulate and test the FPGAs or ASICs completely to be sure that the final hardware will run first time right. Thus needless ASIC mask costs caused by failures and expensive hardware test cycles to find an error can be prevented.
The investment in an efficient design and verification environment is elementary for the quality and predicability of the design process.

The waveform view gives a fast overview about the status of different signals during the simulation. Comfortable integrated design environments like the Aldec Active HDL offers additionally the capability to display the signal status at a give time in block diagrams and state machine diagrams.