HDL Implementation

From technology netlist to the programmed FPGA

After the described RTL model was translated through logic synthesis into a technology dependent netlist which consists of logic elements given by the library of the FPGA vendor, the implementation into an selected FPGA device has to be executed.
With the vendors implementation tools the netlist will be fitted to the internal structures of the FPGA device. Mapping to the physical available structures, placement (location on the silicon) and routing (the connection of the different blocks to each other) are the implementation tasks.

The implementation tools generate the date (for example .bit files) needed for the FPGA programming and the verification (timing information for the simulator).

All major FPGA vendors (Actel, Altera, Lattice and Xilinx) offers their own generic tool flow (simulation, synthesis, mapping, place & route) for the design of FPGA. If a vendor will be replaced by another the designer needs to learn a new flow and new tools.
Integrated design environments (like Aldec Active-HDL) allows to integrate the vendor tools in a generic vendor independent development process. This simplifies the development process and gives the flexibility to choose the FPGA vendor based on the available technology and pricing.