HDL Creation

HDL Design Entry (VHDL oder Verilog)

Using text or graphics for design entry is a matter of designers personal flavor and is also often dependent on the specific project requirements.
Generally all HDL languages are concurrent, means they have a parallel structure. Rather than writing a sequential program a model will created that describes multiple properties of a design which coexists.
Most humans can capture text only line by line but a humans brain can easily realize a parallel graphical structure in a second. Based on that fact a graphical representation of HDL structures makes sense.
Modern flows should give the choice of both representations that the design team can benefit from the advantages of both design entry methods. Typically graphics has major benefits for partitioning and for describing a state machine. The graphical modules will be supplemented by the text based modules.
Of course VHDL and/or Verilog designs can be development completely with the text based approach and lots of designers believe that this is most efficient but typing lines of codes is not the major task. The essential advantages why graphical tools are in use are debugging capabilities, documentation and reusability.
As said, many developers in the concept phase are thinking in structures and state diagrams, searching for failures based on graphics has tremendous benefits.

Advantages of graphical design

• Determination of failures during the concept phase
• Simple and efficient creation of structures
• Preventing design failures.
• Reusability of design block
• Automatic generation of the documentation
• Documentation is by default the actual status of the HDL code

Especially for designers only temporarily developing FPGAs , the graphical approach has substantial advantages. They work the way they are thinking , consequently the learning curve is shortened.

Blockschaltbild in ActiveHDL

Blockdiagram in ActiveHDL

Block diagrams helps to get a fast and easy overview. They are a graphical representations of VHDL and/or Verilog code. ActiveHDL allows to display the status of signals after (or with break points- during) the simulation.

FSM Editor in ActiveHDL

FSM Editor in ActiveHDL

State diagrams enables the easy and fast generation of machines. Also in this case, graphic helps to visualize the VHDL and/or Verilog Code